This invention relates generally to semiconductor device testing, and more particularly the invention relates to a dual channel source measurement unit (SMU) for testing semiconductor device reliability.
A SMU as used for semiconductor reliability testing provides a voltage stress stimulus to a device under test (DUT) and monitors degradation to the DUT caused by the stress stimulus. FIG. 1 is a block diagram of a SMU which includes a digital to analog converter (DAC) 10, gain or amplification block 12, and a resistor network or RNET 14 for measuring current flow to or from the DUT 16 through switch 17. The voltage source DAC 10 and gain unit 12 provide the stress stimulus to DUT 16, while RNET 14 provides monitoring capabilities.
A semiconductor reliability test typically requires the capability to perform the stress and monitor procedures on more than one DUT. This is necessary because calculating reliability information requires statistical analysis with sample sizes large enough that valid conclusions can be drawn. The most practical method of testing many DUTs at one time is to have a multiple output SMU. For example, a single SMU with n outputs can be used instead of n single output SMUs thus decreasing required equipment and cost. It is possible to replace the single output SMUs with one multiple output SMU because some of the required resources on the SMU can be shared among the DUTs. A SMU that fulfills the requirement of multiple outputs is shown in FIG. 2 which includes a DAC 10, gain unit 12, and a plurality of buffers 18 and toggle switches 20, 22 which connect buffers 18 to DUTs 16 and RNET 14 to individual buffers and DUTs.
In this Single Channel Multiple Output SMU configuration the output of the programmable voltage source is connected to buffered sources, which “follow” the output and provide the required voltage to each DUT. The RNET is used to measure current and can be connected to any of the buffered sources to perform measurements on the connected DUTs. This configuration allows resources such as the programmable voltage source and the RNET to be shared among the DUTs.
While the Single Channel Multiple Output SMU configuration does allow multiple DUTs to be tested using a single SMU, it has limitations that impose penalties on certain types of testing. One of the main limitations is the requirement of all connected DUTs to have the same voltage potential applied. This limitation is imposed by having a single programmable voltage source, which all the buffered sources follow. Practically, this means that all the DUTs connected to a SMU must be in their stress or monitor phase at the same time. It would therefore take n times the single DUT measurement time where n is the number of DUTs being tested. Another limitation is that the output power available to each DUT is restricted to that of the buffered sources. Practically, this means the stress and monitor phase of a test are limited to the same power conditions. Finally, in order to make low current measurements (<1 nA) this SMU configuration requires the use of low current leakage buffers which have limitations that would not be present if buffer current leakage was not a factor.
The present invention overcomes these limitations.